1/4 status of this document the japanese version of this doc ument is the formal specification. a customer may use this translation version only for a reference to help reading the formal version. if there are any differences in tr anslation version of this document, for mal version takes priority. rev. a structure silicon monolithic integrated circuit product name irda controller lsi built-in ir remote control model name BU92747KV outer dimension figure 1 outer dimensions features ~ data transfer speed (bps) irda sir: 2.4kbps, 9.6kbps, 19.2 kbps, 38.4kbps, 57.6kbps and 115.2kbps irda mir: 0.576mbps, 1.152mbps irda fir: 4mbps irsimple ~ interface 16-bit data bus , address a 0-3 ~ built-in 2560 2byte fifo buffer (for transmission and reception) ~ accessible as a memory device connected to the bus ~ power down mode setting possible for transmission and reception ~ input clock of 48mhz for external input clock and crystal input clock ~ ir remote control function serial 2-lines sda, and scl *this lsi chip is not subject to radiation-proof design. ? absolute maximum rating ta = 2 5 c unless otherwise stated item symbol minimum maximum unit supply voltage *1 v dd -0.3 2.5 v interface supply voltage1 *1 v io1 -0.3 4.5 v interface supply voltage2 *1 v io2 -0.3 4.5 v input voltage *1 v in -0.3 v io1, 2 +0.3 v power dissipation *2 pd - 900 mw operating temperature range t opr -40 85 c storage temperature range t stg -55 125 c *1 it applies to all pins based on the gnd pin. *2 reduced by 9.0mw for each increase in ta of 1 ? over 25 ? (mounted on 70.0mm 70.0mm 1.6mm glass-epoxy pcb) ? operation range item symbol minimum st andard maximum unit supply voltage v dd 1.62 1.8 1.98 v interface supply voltage1 v io1 1.62 1.8 3.6 v interface supply voltage2 *3 v io2 1.62 1.8 3.6 v *3 v io2 is connected with xin/clk48m, xout, pwdn, nirq and reset.
2/4 rev. a ? electrical characterist ics (dc characteristics) ta = 2 5 c, v dd =1.8v, v io1 =1.8v, v io2 =1.8v and gnd=0v unless otherwise stated standard value item symbol min typ max unit remarks dissipation current 1 i dd 1 - 0.1 10 a for input with no output load = 0v dissipation current 2 i dd 2 - 10 30 ma for xin = 48mhz digital high-level input voltage v ih 0.75 v io - - v digital low-level input voltage v il - - 0.25 v io v - - 10 a input voltage level 1.8v digital high-level input current i ih - - 100 a input voltage level 1.8v test1-3 digital low-level input current i il - - 10 a input voltage level gnd digital high-level output voltage v oh v io -0.6 - - v intr, d 0-15 , irdapwdown, irtx, irrc, nirq, ctla ioh=-1ma digital low-level output voltage v ol - - 0.6 v intr, d 0-15 , irdapwdown, irtx, irrc, sda, nirq, ctla iol=1ma ? pin description pin name i / o condition of after reset pin function circuit diagram irrx i - irda receive input pin b extir i - signal input pin in sm2="h" (input signal is outputted to irtx or irrc) b irtx o l irda and remote control transmission output pin transmission irda when rc_en= "l" transmission remote control when rc_en="h", rc_mode="h" a d 0-15 i / o input data i/o pin c a 0-3 i - address input pin b cs i - chip select pin. low (l) active the read/write signal goes ?active? in a low period. b rd i - read signal input pin. low (l) active b wr i - write signal input pin. low (l) active b intr o h cpu interrupt request output pin (irda controller) the signal goes ?low? when an interrupt condition takes place. a reset i - reset input pin. low (l) active the signal causes the internal regist er settings, etc. to be initialized. b pwdn i - power down mode setting. low (l) active when set to low (l), this signal causes the wait status and sets the low dissipation current mode. after the power down mode is removed, reset=l must set to low until crysta l clock oscillatio n becomes stable (about 2 or 3 ms). after that reset must set to high. take it into consideration that this period depends on the crystal in use. b irrc o l remote control transmission output pin transmission remote control when rc_en= "h", rc_mode= "l" a ctla o l control signal output pin a scl i - serial clock f sda i/o input serial data i/o pin g nirq o h cpu interrupt request output pin (ir remote control) the signal goes ?low? when an interrupt condition takes place. a xin/clk48m i - crystal in / external clk input e xout o - crystal out (n.c when external input clock is used) e test1-3 i - test pins (these pins must be gnd during normal operation.) d irda pwdown o h irda module control signal output pin these pins must be open for irda modules having no power-down pin. a v dd - - power supply pin - v io1 - - interface power supply voltage1 - v io2 - - interface power supply voltage2 - gnd - - ground pin -
3/4 rev. a ? equivalent circuit diagram ? outer dimensions figure1 outer dimensions(vqfp48) pin no. pin name pin no. pin name pin no. pin name pin no. pin name 1 pwdn 13 gnd 25 d 0 37 gnd 2 reset 14 d 5 26 d 6 38 irrx 3 nirq 15 a 0 27 d 14 39 extir 4 v io2 16 d 4 28 d 12 40 irtx 5 test2 17 d 10 29 d 13 41 irdapwdown 6 a 3 18 d 9 30 intr 42 ctla 7 v io1 19 d 3 31 cs 43 irrc 8 test1 20 d 15 32 test3 44 (nc) 9 a 2 21 d 2 33 rd 45 scl 10 a 1 22 d 8 34 v io1 46 sda 11 d 11 23 d 1 35 wr 47 xout 12 v dd 24 d 7 36 v dd 48 xin " 9 * / 9 0 6 5 1 8 % / # $ % & ' ( (unit : mm) lot no. u92747kv
4/4 rev. a ? notes for use (1) absolute maximum ratings use of the ic in excess of absolute maximum ratings su ch as the applied voltage or operating temperature range may result in ic damage. assumptions should not be made regarding the state of the ic (short mode or open mode) when such damage is suffered. a physical safety measure such as a fuse should be implemented when use of the ic in a special mode where the absolu te maximum ratings may be exceeded is anticipated. (2) mutual impedance use short and wide wiring tracks for the power supply and ground to keep the mutual impedance as small as possible .use a capacito r to keep ripple to a minimum. (3) gnd potential ensure a minimum gnd pin potential in all operating conditions. (4) short circuit mode between terminals and wrong mounting in order to mount the ic on a set pcb, pay thorough attention to the direction and offset of the ics. erroneous mounting can destroy the ic. furthermore, if a short ci rcuit occurs due to foreign matters entering between terminals or between the terminal and the power supply or the gnd terminal, the ic can destroy (5) setting of heat use a thermal design that allows for a sufficient margin in light of the power dissipation (pd) in actual operating conditions. (6) actions in strong magnetic field use caution when using the ic in the presence of a st rong magnetic field as doing so may cause the ic to malfunction. (7) ground wiring pattern when using both small signal and large current gnd patte rns, it is recommended to isolate the two ground patterns, placing a single ground point at the applic ation's reference point so that the pattern wiring resistance and voltage variations caused by large curre nts do not cause variations in the small signal ground voltage. be careful not to change the gnd wiring pattern of any external components, either. (8) when power is first supplied the cmos ic, it is possibl e that the internal logic may be unstable and rush current may flow instantaneously. therefore, give special c onsideration to power coupling capacitance, power wiring, width of gnd wiring, and routing of connections. (9) for ics with more than one power, it is possible than rush current many flow instantaneously due to the internal powering sequence and delays. therefore, give special consideration to power coupli ng capacitance, power wiring, width of gnd wiring, and routing of wiring.
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